Matt Sinclair
Research Scientist at University of Wisconsin-Madison
Madison, Wisconsin, United States
Summary
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RockstarMatt Sinclair is a research scientist and assistant professor-level engineer based in Madison, Wisconsin with nine years of hands-on experience in computer architecture and performance engineering. He contributes to the prominent gem5 system simulator, where he focuses on GCN3 backend enhancements—adding unaligned memory access support, optimizing SDWA/DPP instruction flows, and implementing multi-dword MUBUF operations and HSA barrier synchronization. His work blends low-level simulation fidelity with practical performance fixes, revealing a knack for turning intricate ISA features into reliable, testable simulator behavior. Known for tackling subtle memory and synchronization edge cases, he bridges academic rigor with production-quality engineering in open-source infrastructure.
9 years of coding experience
Github Skills (12)
memory-management10
c-language10
cprogramming-language10
performance-optimization10
computer-architecture10
simd9
multithreading8
parallel-computing8
open-source7
x865
x86-645
risc-v5
Programming languages (10)
Github contributions (5)
gem5/gem5
Mar 2018 - Jan 2023
The official repository for the gem5 computer-system architecture simulator.
Role in this project:
Backend Developer & Performance Engineer
Backend Developer & Performance EngineerContributions:442 reviews, 15 commits, 43 PRs in 4 years 10 months
Contributions summary:Matt's contributions primarily focus on enhancing the performance and functionality of the gem5 computer-system architecture simulator, specifically within the GCN3 architecture module. They added support for unaligned memory accesses, which involved modifying existing code and adding helper functions to handle various memory request types. The user also fixed bugs and implemented new features related to the Single Data, Wide Accumulation (SDWA) and Direct Pixel Processing (DPP) instructions within the GCN3 architecture, streamlining the execution flow of these instructions. Furthermore, the user has implemented multi-dword buffer loads and stores for MUBUF instructions and has provided support for HSA's barrier bit kernel synchronization.
storedsimulationupstreamsimulatorgem5-simulator
mattsinc/heterosync
Jun 2018 - Nov 2022
HeteroSync is a benchmark suite for performing fine-grained synchronization on tightly coupled GPUs
Contributions:45 commits, 3 PRs, 52 pushes in 4 years 5 months
cudampibenchmark-suitesynchronizationgpu
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