Matt Venn
Founder at Tiny Tapeout
Valencia, Valencian Community, Spain
Summary
🤩
Rockstar🎓
Top SchoolMatt Venn is a founder and engineer with 15 years' experience making ASIC design accessible to hobbyists, students, and professionals from his base in Valencia. He co-founded Tiny Tapeout and authored the Zero to ASIC course, together enabling thousands to take designs from first concept to manufactured microchips. At YosysHQ he leads sales and communication for a core open-source synthesis and formal verification toolchain, while contributing hands-on to projects like OpenLane and Tiny Tapeout integrations that bridge RTL-to-GDSII automation and educational workflows. His background spans embedded firmware, automation, and hardware education—from contributing firmware fixes for open-source keyboard projects to building tooling that surfaces techmap and synthesis internals for learners. Known for combining clear science communication with practical engineering, he has a track record of turning complex ASIC flows into approachable, reproducible experiences.
15 years of coding experience
8 years of employment as a software developer
Bachelor of Science - BS Electrical and Electronics Engineering, Bachelor of Science - BS Electrical and Electronics Engineering at University of Leeds
Stackoverflow
1reputation
181reached
1answer
1question
Github Skills (22)
verilog10
c-language10
python10
firmware10
led-controller10
avr10
asic10
sys10
rt10
arm10
embedded10
cprogramming-language10
tcl10
vlsi9
yosys9
Programming languages (26)
Github contributions (5)
TinyTapeout/tt02-submission-template
Oct 2022 - Dec 2022
Submission template for TT02
Role in this project:
Embedded Systems Engineer / Automation Engineer
Embedded Systems Engineer / Automation EngineerContributions:7 reviews, 71 commits, 9 PRs in 1 month
Contributions summary:Matt primarily contributed to the project by modifying configuration files and scripts for the TinyTapeout project. They added and modified Tcl configuration files for OpenLane, updated Python scripts for generating project setup, and enhanced the configuration of the design environment. The user also integrated the project with Wokwi by fetching the necessary diagram and Verilog code from the Wokwi platform. The updates included adding Cocotb based testbench.
asictemplategdstapeout
The-OpenROAD-Project/OpenLane
Jul 2020 - Nov 2021
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Role in this project:Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:3 reviews, 8 commits, 12 PRs in 1 year 3 months
Contributions summary:Matt contributed to the design of an inverter and a manual macro placement test within the OpenLane flow. Their work included writing Verilog code for the inverter, adding configuration settings, and including license information. Additionally, the user modified synthesis scripts to create dot files, enhancing the ability to examine the techmap process, which is crucial for understanding the process of RTL to GDSII flow.
yosysasic130nmmagicnetgen
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