Matt Weber
Senior Developer at Akuna Capital
Altoona, Wisconsin, United States
Summary
👤
Senior🎓
Top SchoolMatt Weber is a Senior Developer and ASIC/FPGA architect with over 20 years designing high-performance processor, networking, and storage silicon and reusable IP across technologies from 180nm to 22nm. He blends deep microarchitecture and CAD tool expertise (simulation, synthesis, STA, LEC, formal) with hands-on FPGA acceleration, SoC modeling, and hardware/software integration for customers and product teams. As a consultant and technical lead he has shipped complex IP like Interlaken and an HMC host controller, led product architecture for an Arduino-compatible FPGA board, and managed customer-facing releases and CAD flows. Comfortable moving between low-level RTL, system architecture, lab debug, and production test automation, he has a track record of turning research-grade designs into parameterized, manufacturable IP. Based in Altoona, WI, he pairs academic grounding (MS EE) with practical innovation and a knack for simplifying CAD and release processes that accelerate time-to-market.
10 years of coding experience
25 years of employment as a software developer
BS, Electrical Engineering, BS, Electrical Engineering at Michigan Technological UniversityMS, Electrical Engineering, MS, Electrical Engineering at University of Minnesota
Github Skills (3)
ide10
arduino-ide9
arduino9
Programming languages (5)
Github contributions (5)
AloriumTechnology/XLR8Servo
Jan 2016 - Jul 2016
Contributions:2 releases, 5 pushes, 1 branch in 5 months
AloriumTechnology/XLR8NeoPixel
Nov 2015 - Mar 2016
Contributions:1 release, 10 commits, 7 pushes in 3 months
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