Matteo Perotti
Senior RTL Engineer at Tenstorrent
Zurich, Zurich, Switzerland
Summary
👤
Senior🎓
Top SchoolMatteo Perotti is a Senior RTL Engineer with eight years of experience in computer architecture and low-level hardware design, currently at Tenstorrent after a research-rich tenure at ETH Zürich and PULP Platform. He has hands-on expertise improving RISC-V cores and vector units—contributing bug fixes, dispatcher enhancements, MMU/TLB work and prefetch/misaligned-instruction handling across well-known open-source projects like CVA6, CV32E40P and Ara. Known for pairing rigorous academic training (ETH Zürich PhD work and top honors from Politecnico di Torino) with pragmatic engineering, he focuses on correctness, performance and integration testing. A people-oriented problem solver who enjoys tackling technical puzzles, he brings both system-level insight and low-level implementation discipline to complex processor and embedded systems challenges.
8 years of coding experience
Doctor of Science, Electronic Engineering and Computer Architecture, Doctor of Science, Electronic Engineering and Computer Architecture at ETH ZürichMaster's Degree, Electronic Engineering, Electronic Systems, 110/110 cum Laude, Master's Degree, Electronic Engineering, Electronic Systems, 110/110 cum Laude at Politecnico di Torino
English, Italian, French, German
Stackoverflow
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Github Skills (20)
hardware-designs10
verilog10
systemverilog10
risc-v10
cpu10
cpu-architecture10
vectordb10
vector10
asic10
sys10
systemverilog-hdl10
embedded10
assembly9
hdl9
fpga9
Programming languages (9)
Github contributions (5)
pulp-platform/ara
Jan 2021 - Jan 2023
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
Role in this project:
Back-end & Hardware Engineer
Back-end & Hardware EngineerContributions:132 reviews, 1095 commits, 226 PRs in 2 years
Contributions summary:Matteo contributed to the Ara platform's hardware implementation by adding support for various instructions, including multiply and multiply-add, as well as widening and integer arithmetic reduction operations. Their work included modifying the dispatcher to handle these new instructions, refactoring components to improve performance, and fixing critical bugs. The user also implemented new software utilities and performed integration testing to enable the running of software benchmarks with a perfect dispatcher.
cpurisc-vasic64-bitcoprocessor
openhwgroup/cv32e40p
Mar 2020 - Aug 2020
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Role in this project:Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:8 reviews, 55 commits, 6 PRs in 4 months
Contributions summary:Matteo primarily focused on low-level modifications and testing within the RISC-V CPU project. They implemented fixes for misaligned instructions in the `riscv_aligner` module, added memory stall tests to the custom test environment, and improved the prefetch buffer. Their contributions indicate a focus on ensuring correct instruction handling and memory access behavior, which is essential for a processor's functionality.
risc-vcpupulpuvmriscv
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