Matthew Bridges is a Senior FPGA Design Engineer with 13 years of experience designing high-performance, low-latency digital systems and RTL in VHDL and SystemVerilog. He has shipped production IP and firmware for PCIe, Ethernet, CoaXPress and high-speed transceivers across roles at Intel, Active Silicon and Oriole Networks, and has led small teams and release cycles for complex hardware products. Comfortable across hardware, embedded Linux and cloud-enabled DevOps, he has hands-on experience with RFSoC platforms, advanced timing closure and verification using OSVVM and Aldec tools. Matthew enjoys pushing customized computing boundaries and solving challenging timing and throughput problems that demand both architectural foresight and meticulous implementation. Based in London, he combines rigorous engineering discipline with a professional presentation and a focus on quality deliverables. An early-career educator, he also brings practical mentoring experience from university teaching to his engineering leadership.
13 years of coding experience
10 years of employment as a software developer
Bachelor’s Degree Electrical & Computer Engineering, Bachelor’s Degree Electrical & Computer Engineering at University of Cape Town
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