Matthew Bridges

Senior FPGA Design Engineer at Oriole Networks

London, England, United Kingdom
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Summary

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Senior
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Top School
Matthew Bridges is a Senior FPGA Design Engineer with 13 years of experience designing high-performance, low-latency digital systems and RTL in VHDL and SystemVerilog. He has shipped production IP and firmware for PCIe, Ethernet, CoaXPress and high-speed transceivers across roles at Intel, Active Silicon and Oriole Networks, and has led small teams and release cycles for complex hardware products. Comfortable across hardware, embedded Linux and cloud-enabled DevOps, he has hands-on experience with RFSoC platforms, advanced timing closure and verification using OSVVM and Aldec tools. Matthew enjoys pushing customized computing boundaries and solving challenging timing and throughput problems that demand both architectural foresight and meticulous implementation. Based in London, he combines rigorous engineering discipline with a professional presentation and a focus on quality deliverables. An early-career educator, he also brings practical mentoring experience from university teaching to his engineering leadership.
code13 years of coding experience
job10 years of employment as a software developer
bookBachelor’s Degree Electrical & Computer Engineering, Bachelor’s Degree Electrical & Computer Engineering at University of Cape Town
languagesEnglish
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Github Skills (15)

prototyping7
rhino7
architecture6
vhdl6
vivado4
ctags4
vscode3
systemverilog3
iverilog2
vscode-extension2
hdl2
modelsim2
verilator2
verilog2
language-server1

Programming languages (2)

TypeScriptVHDL

Github contributions (5)

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matthewbridges/dugong

Aug 2012 - Oct 2020

A VHDL Architecture for Digital Radio prototyping on the RHINO Platform
Contributions:362 commits, 5 PRs, 17 pushes in 8 years 3 months
vhdlprototypingdigital-radioradioarchitecture
SDRG-UCT/u-boot_rhino

Sep 2015 - Jun 2016

Contributions:3 pushes in 8 months
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