Matthew Papageorge
BIOS Developer at NVIDIA
Austin, Texas, United States
Summary
👤
Senior🎓
Top SchoolMatthew Papageorge is a BIOS and firmware engineer with nine years of deep experience building UEFI, FSP, and coreboot solutions for x86 and ARM platforms, currently developing SBIOS at NVIDIA. He has led large-scale BIOS rollouts at AWS—replacing vendor firmware across ~800k servers—and contributed platform support for AMD Picasso/Cezanne in the coreboot tree, including power-saving PCIe features and EFS SPI configurations. Comfortable at the intersection of hardware and software, he routinely debugs silicon and PCIe issues with protocol analyzers, oscilloscopes, and AMD IOMMU expertise, and writes production C daily. His background spans server OEM work at HPE, AGESA/UEFI IOMMU drivers at AMD, and hands-on accelerator platform development for NVIDIA, AMD and Inferentia2. Based in Austin, he pairs low-level firmware craftsmanship with practical deployment and operational experience across hyperscale fleets.
9 years of coding experience
12 years of employment as a software developer
Bachelor of Science Electrical and Computer Engineering, Bachelor of Science Electrical and Computer Engineering at The University of Texas at Austin
Github Skills (12)
c1710
firmware10
embedded10
c1110
sys10
boot10
pcie9
device-tree8
amd8
acpi8
system-configuration7
power-management7
Programming languages (4)
Github contributions (5)
coreboot/coreboot
Nov 2019 - Nov 2021
Read-only mirror of https://review.coreboot.org/coreboot.git. Synced every hour. We don't handle Pull Requests.
Role in this project:
Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:21 commits in 1 year 11 months
Contributions summary:Matthew's primary contributions focused on modifying and configuring coreboot for AMD Picasso and Cezanne platforms. They added support for platform-specific features, including setting up the Embedded Firmware Structure (EFS) SPI configurations, enabling power-saving features like PCIe ASPM and clock gating, and modifying devicetrees. The changes involved modifying platform descriptors and UPD headers. Their work also included integrating PCIe reset GPIOs to improve system stability during resume.
corebootfirmwarereviewpull-requestsbootloader
matthewpapa07/InfraredKitForRPI
Oct 2016 - Mar 2017
Contributions:3 pushes, 1 branch in 5 months
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