Matthew Walker
Senior MTS at Cerebras
Redmond, Washington, United States
Summary
👤
Senior🎓
Top SchoolMatthew Walker is a Senior MTS with 12 years of experience designing and shipping low-level software for hardware accelerators, FPGAs, and ML runtimes, currently based in Redmond. He has progressed from FPGA CAD and compiler back-ends to production ML runtime and PyTorch backend work at Microsoft and now accelerator systems at Cerebras. His research-driven approach (including a U of T masters project that produced a 40x runtime improvement for mapping compilers) informs pragmatic engineering: optimizing heuristics, data structures, and debugging ergonomics in large C/C++ codebases. An active open-source contributor, he’s improved usability and visualization in the well-known verilog-to-routing project, demonstrating attention to both developer UX and visual clarity. Colleagues describe him as someone chasing “actual experience” in the long-term problems he wants to solve, blending deep systems knowledge with hands-on implementation.
12 years of coding experience
9 years of employment as a software developer
Master's degree, Computer Engineering, Master's degree, Computer Engineering at University of Toronto
Stackoverflow
1,300reputation
541kreached
15answers
4questions
Github Skills (15)
c1710
fpga10
verilog10
c1110
eda10
enviroment9
cad9
powershell6
windows6
homebrew6
cmake6
bison6
webhosting6
ssh6
scripting6
Programming languages (7)
Github contributions (5)
verilog-to-routing/vtr-verilog-to-routing
May 2014 - Sep 2017
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Role in this project:
Back-end Developer
Back-end DeveloperContributions:51 commits, 3 PRs in 3 years 5 months
Contributions summary:Matthew made several commits focused on improving the error messages within the `pb_type_graph.c` file, clarifying and refining the text for better debugging and user understanding. Additionally, the user altered the color scheme of the graphics, including fan-in nets, to enhance readability and visual clarity of the diagrams. Finally, the user modified the source code to support display of sub-blocks.
vtrcadedaplacementsynthesis
golvok/verilog_preprocessor
Aug 2014 - Dec 2016
Contributions:18 commits, 1 push in 2 years 4 months
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