Summary
Mattia Rizzi is a Senior Electronics Engineer based in Villigen, Switzerland, with a decade of hands-on experience designing FPGA-based systems for precision timing, RF synthesis, and radiation-tolerant applications. At Paul Scherrer Institut and previously at CERN, he led the development of ultra-low jitter RF front-ends and mixed-signal PCBs—delivering sub-femtosecond synchronization for SwissFEL and sub-100 fs RMS time-transfer proofs of concept. His skill set spans VHDL/HDL SoC design, high-speed SerDes, White Rabbit deterministic networking, and RF clock synthesis and characterization using DSO, phase-noise analyzers and VNAs. He combines academic rigor (PhD in Electronics Engineering) with practical product delivery, from handheld industrial network analyzers to space-tolerant RISC-V SoCs proven up to 500 Gy TID. Colleagues rely on him for solving the hardest timing, jitter and RF distribution problems where analog layout and digital firmware must be co-designed. Notably, he repeatedly bridges research and production, turning novel synchronization algorithms into deployable hardware.
10 years of coding experience
3 years of employment as a software developer
Bachelor's degree, Information Technology, 101/110, Bachelor's degree, Information Technology, 101/110 at Università degli Studi di Brescia
Perito elettronico, Maturità, Perito elettronico, Maturità at ITIS B. Pascal - Manerbio
Italian, English, French