Maxim Polyakov
Senior Software Engineer at Y.A.D.R.O. Company
Moscow, Moscow, Russia
Summary
👤
Senior🎓
Top SchoolMaxim Polyakov is a Senior Software Engineer with 7+ years of deep, hands-on experience in firmware and systems software across x86/PowerPC/ARM/RISC-V platforms, currently driving embedded and DCIM backend development at Y.A.D.R.O. He combines low-level expertise (ASM/C/C++, Linux kernel/user space, boot firmware like coreboot/SeaBIOS/EDK2) with higher-level Go and Qt work, delivering solutions for storage (NVMe, RAID/erasure coding), networking (PCIe, switches/routers/CPE) and SDR/IoT devices. A prolific open-source contributor to coreboot, he has added real hardware support (e.g., Skylake, Xeon E3, H110) and PCIe Gen3 enablement, showing a rare blend of platform bring-up and system integration skills. His background also spans RTOS and firmware for RAID controllers, PNOR/hostboot stacks, and FPGA development, reflecting a broad embedded toolchain fluency. Colleagues describe him as a research-minded engineer who seeks novel solutions for future projects while shipping robust production code.
7 years of coding experience
6 years of employment as a software developer
Master's degree, Electronics and Microelectronics, Master's degree, Electronics and Microelectronics at Moscow Power Engineering Institute (Technical University)
Stackoverflow
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Github Skills (14)
c1710
firmware10
cpu-architecture10
gpio10
device-tree10
c1110
intel10
boot10
computer-architecture10
architecture10
acpi9
pcie9
assembly8
x868
Programming languages (5)
Github contributions (5)
coreboot/coreboot
Feb 2019 - May 2022
Read-only mirror of https://review.coreboot.org/coreboot.git. We don't handle Pull Requests.
Role in this project:
Back-end Developer & Firmware Engineer
Back-end Developer & Firmware EngineerContributions:148 commits in 3 years 3 months
Contributions summary:Maxim primarily contributed to the coreboot firmware development for the coreboot/coreboot repository, adding support for new hardware like Intel Xeon E3, i5-6600 (Skylake) and H110 chipset. Their work involved modifying the baseboard and device tree configuration to enable PCIe Gen3 support, and setting up the GPIO configuration for the SuperIO chip. They also implemented improvements for the IGD and memory allocation.
corebootfirmwarereviewpull-requestsbootloader
maxpoliak/pch-pads-parser
May 2019 - Aug 2020
A small utility for analyzing the PCH GPIOs config from inteltool log file
Contributions:236 commits, 28 PRs, 86 pushes in 1 year 3 months
analyzinglog-fileconfigparserlex
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