Meera Ramesh is a Senior System Software Engineer based in San Jose with a decade of experience focused on GPU testing, performance validation, and systems-level data analysis. At NVIDIA she builds test infrastructure and tooling to validate GPU health, power/voltage/clock behavior, and to normalize heterogeneous test outputs for shipping-quality assurance. Her background includes embedded and RFIC software on ARM/FPGA platforms and a CUDA-driven Master's thesis on GPU-based deep packet inspection, giving her a rare blend of low-level hardware insight and parallel-software optimization. Comfortable across C/C++, CUDA, and data pipelines, she pairs rigorous measurement-driven validation with practical automation to move silicon from lab to production.
10 years of coding experience
1 year of employment as a software developer
San José State University
Bachelor’s Degree, Electronics and Communications Engineering, 3.87/4, Bachelor’s Degree, Electronics and Communications Engineering, 3.87/4 at NMAM INSTITUTE OF TECHNOLOGY
Contributions:775 pushes, 14 branches in 11 months
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