Megan Wachs
VP Of Engineering at SiFive
Palo Alto, California, United States
Summary
🤩
Rockstar🎓
Top School
Top expert inDigital Hardware Design and Verification
Megan Wachs is a VP of Engineering with over a decade of experience building silicon and tooling for the RISC-V ecosystem, leading efforts to democratize custom silicon at SiFive. With a Stanford PhD in Electrical Engineering and deep roots in ASIC, FPGA prototyping, and cryptographic hardware, she blends rigorous research-driven design with hands-on RTL and firmware development. She authored Chisel RTL for SiFive’s Freedom platform and contributed to flagship open-source projects like Spike and riscv-tests, improving simulator debug and test infrastructure used across the RISC-V community. Megan has led cross-disciplinary teams on security-focused ASICs and shepherded platform bring-up from PCB to 32-core transactional coherence hardware—skills that inform her pragmatic approach to platform and toolchain engineering. Passionate about open source and diversity, she pairs technical depth with leadership that scales hardware accessibility for broader developer audiences.
10 years of coding experience
8 years of employment as a software developer
ScB, Engineering, ScB, Engineering at Brown UniversityHHSMaster's Degree, Electrical Engineering, Master's Degree, Electrical Engineering at Stanford University
Github Skills (36)
debugging10
debug10
assembly10
python10
testing10
risc-v10
interrupt-handling10
firrtl10
c1110
device-emulation10
scala10
c1710
gpio10
gdb10
sys10
Programming languages (10)
Github contributions (5)
chipsalliance/chisel
Aug 2016 - Jan 2023
Chisel: A Modern Hardware Design Language
Role in this project:
Backend Developer & Test Automation Engineer
Backend Developer & Test Automation EngineerContributions:1504 reviews, 192 commits, 121 PRs in 6 years 6 months
Contributions summary:Megan contributed to the Chisel hardware design language repository by implementing and testing features related to clock type connections and other internal functionalities. They added missing cases and test cases for connecting ClockType, demonstrating a focus on ensuring the correctness and reliability of the language's type system. Furthermore, the user's contributions include merging branches and fixing scaladoc for a specific target, which involved improving documentation and code integration. Their work involved modifications across different files, primarily in the `firrtl` and `chisel` directories and contributed to the overall development and quality assurance of the Chisel language.
rtlasicvhdllanguage-designeda
riscv-software-src/riscv-tests
Aug 2016 - Sep 2018
Role in this project:Back-end & Automation Engineer
Back-end & Automation EngineerContributions:51 commits, 25 PRs, 27 pushes in 2 years 1 month
Contributions summary:Megan primarily contributed to the test infrastructure of the RISC-V software project. Their commits focused on enhancing the GDB server and testlib utilities, adding support for simulator targets, and refining the testing process. They implemented improvements to the test setup, including adjustments for running tests with specific configurations and addressing issues related to out-of-reset behavior. Additionally, the user made changes to various test programs, indicating involvement in adapting existing code to the testing framework and potentially addressing compatibility concerns.
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