Melcher Elmar
Specialist at Universidade Federal de Campina Grande
Campina Grande, Paraíba, Germany
Summary
👤
Senior🎓
Top SchoolMelcher Elmar is a specialist in integrated circuit and FPGA design with a decade of hands-on experience focused on functional verification and digital signal processing. He combines academic depth—as a long-standing professor at Universidade Federal de Campina Grande and a Doctorate in Microelectronics from Télécom Paris—with industry practice at ALTEN and ALTEN Germany, where he advances hardware-software co-design efforts. His open-source contributions include enhancements to the widely used RISC-V ISA simulator Spike, improving cross-width (32/64-bit) value display, exception handling, and debug I/O using Boost libraries—demonstrating attention to tooling and reproducible debugging. He has led technology programs and served as CTO and technical coordinator in Brazilian research and IP initiatives, bringing both strategic leadership and low-level engineering rigor. Based in Campina Grande with ties to Germany, he blends international research pedigree with practical embedded systems and verification expertise.
10 years of coding experience
9 years of employment as a software developer
Doctor's Degree, Microelectronics, Doctor's Degree, Microelectronics at Télécom Paris
Stackoverflow
1reputation
0reached
1answer
0questions
Github Skills (15)
simulations10
simulation10
risc-v10
c-language10
cprogramming-language10
boost10
simulator10
debug9
socket9
socket-io9
debugging9
configuration-management8
makefile7
gnu-make7
spike6
Programming languages (6)
Github contributions (5)
riscv-software-src/riscv-isa-sim
Apr 2021 - Nov 2021
Spike, a RISC-V ISA Simulator
Role in this project:
Back-end Developer
Back-end DeveloperContributions:33 reviews, 19 commits, 11 PRs in 7 months
Contributions summary:Melcher contributed to the RISC-V ISA simulator, Spike, by modifying the code to improve the display of 32-bit values. These changes included adjusting the display format based on the maximum XLEN, updating exception handling, and modifying output formatting to support both 32-bit and 64-bit architectures. The user also integrated Boost libraries, specifically for socket input/output streams and command-line options, enhancing the simulator's functionality and debugging capabilities. Additionally, they added a feature to read debug commands from a file.
risc-visariscvriscv32simulator
emelcher/riscv-isa-sim
Apr 2021 - Feb 2022
Spike, a RISC-V ISA Simulator
Contributions:104 pushes, 9 branches in 9 months
risc-visariscvsimulatorrisc
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