Michael Hartman is an Application Engineer Architect with 15+ years specializing in implementation and backend flows for ASIC and SoC design, currently at Cadence. He has driven STA, floorplanning, low-power synthesis, DFT, APR, and formal equivalence across 10+ tapeouts and multiple process nodes, often owning full-chip sign-off flows and kit development methodologies. Equally comfortable in tooling and hands-on design, he builds automation and developer-friendly flows using Python, TCL, Bash and Makefiles to accelerate teams and reduce manual effort. His background at Intel and Cisco includes creating partition budgeting GUIs, LSF and network administration for compute farms, and designing prototype FPGA/PCB test boards—skills that reveal a systems-level perspective beyond pure RTL. A frequent mentor who enjoys teaching junior engineers, he blends deep technical craft with practical dev-ops discipline to deliver predictable QOR and timely tapeouts.
15 years of coding experience
21 years of employment as a software developer
BS, Computer Engineering, BS, Computer Engineering at Auburn University
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