Michael Rogenmoser
SoC Design Engineer at ETH Zürich
Zürich Metropolitan Area Switzerland
Summary
🤩
Rockstar🎓
Top SchoolMichael Rogenmoser is a SoC design engineer with 12 years of experience, currently working at Tenstorrent and pursuing PhD research at ETH Zürich on fault-tolerant multicore architectures for space and reliable SoCs. He combines hands-on RTL and verification work—contributing to PULP Platform projects such as AXI SystemVerilog IP and the PULPissimo top-level system—with embedded and automation expertise that spans JTAG/testbench optimization and cross-core compatibility fixes. Previously he led electrical engineering for a Hyperloop pod and has taught digital and electronic circuits, blending leadership, practical system-level integration and pedagogy. Based in Zürich, he is an active open-source contributor focused on making high-performance on-chip communication IP more modular and maintainable—an uncommon mix of academic depth and production-grade hardware engineering.
12 years of coding experience
2 years of employment as a software developer
Bilingual Matura, Physics and Mathematics, 5.23, Bilingual Matura, Physics and Mathematics, 5.23 at Mathematisch- Naturwissenschaftliches Gymnasium RämibühlMaster of Science - MS, Electrical Engineering and Information Technology, Master of Science - MS, Electrical Engineering and Information Technology at ETH ZürichBachelor of Science - BS, Electrical and Electronics Engineering, 5.49, Bachelor of Science - BS, Electrical and Electronics Engineering, 5.49 at ETH ZurichThe University of Melbourne
German, English
Github Skills (20)
verilog10
systemverilog10
axi410
hardware10
ax10
sys10
rt10
fpga10
embedded10
jtag9
hardware-designs9
ip9
automations8
automation8
risc-v8
Programming languages (10)
Github contributions (5)
pulp-platform/axi
Jan 2021 - Nov 2022
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Role in this project:
Backend & Hardware Engineer
Backend & Hardware EngineerContributions:4 releases, 49 reviews, 78 commits in 1 year 10 months
Contributions summary:Michael primarily focused on updating and maintaining the AXI SystemVerilog IP modules and verification infrastructure. Their contributions involved updating modules from `common_verification` and `common_cells` dependencies, indicating a focus on maintaining the integrity of the project's dependencies. This included changes to testbenches and related configurations across multiple test files, such as `tb_axi_cdc.sv`. Additionally, the user added interface variants to the modules to improve the modularity of the core AXI modules.
rtlsystemverilogvlsifpgaaxi4
pulp-platform/pulpissimo
Jan 2021 - Jun 2022
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
Role in this project:Embedded Systems Engineer / Automation Engineer
Embedded Systems Engineer / Automation EngineerContributions:5 reviews, 21 commits, 9 PRs in 1 year 4 months
Contributions summary:Michael's contributions primarily focused on improving the PULPissimo platform's hardware design and simulation environment. They addressed compatibility issues for different core types (RISCY and IBEX), declared missing signals, and fixed errors in the build and execution processes. The user also optimized the JTAG loading task within the testbench, improving efficiency and speed of the testing process.
pulpcpusocdomainelectrical-engineering
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