Michael West
San Jose, California, United States
Summary
🤩
Rockstar🎓
Top SchoolMichael West is a seasoned principal software and firmware engineer with over two decades of experience bringing up hardware and building high-performance embedded, FPGA, and SDR systems. Based in San Jose, he led development and maintenance of the open-source UHD driver and USRP FPGA cores at Ettus Research, directly resolving critical low-level bugs and improving PPS, timing, and streaming performance for Ethernet, PCIe and USB transports. He combines RF analog and DSP expertise—covering superheterodyne and direct-conversion radios, MIMO, TDD/FDD and phased arrays—with pragmatic troubleshooting that has unlocked millions in customer orders. Equally comfortable in C/C++, Python and Java across Windows and Linux, he has a track record of marrying short-term creative fixes with prioritized long-term feature and quality improvements. Not obvious from titles alone: he’s often the bridge between product management, manufacturing and global support teams, creating automated tests and calibration tools that turn prototype hardware into reliable production systems.
12 years of coding experience
20 years of employment as a software developer
Bachelor of Science (BS), Computer Engineering, Bachelor of Science (BS), Computer Engineering at DeVry University-California
Github Skills (21)
debugging10
verilog10
debug10
c-language10
firmware10
time-management10
pg10
clock10
device-driver10
driver10
sys10
fpga10
hdl10
embedded10
cprogramming-language10
Programming languages (3)
Github contributions (5)
EttusResearch/fpga
Feb 2014 - Sep 2021
The USRP™ Hardware Driver FPGA Repository
Role in this project:
Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:90 commits, 5 PRs, 29 pushes in 7 years 8 months
Contributions summary:Michael primarily focused on modifications within the FPGA hardware driver repository, specifically addressing issues related to the USRP™ Hardware Driver FPGA Repository. Their contributions centered on implementing and refining the Pulse Per Second (PPS) logic within the FPGA core, including the integration of internal PPS generation, external input selection, and LED control. Furthermore, the user addressed bugs related to clock and Ethernet control and performance.
xilinxlatticeusrphardwarefpga
EttusResearch/uhd
Oct 2013 - Jan 2023
The USRP™ Hardware Driver Repository
Role in this project:Backend & Embedded Systems Engineer
Backend & Embedded Systems EngineerContributions:12 releases, 620 commits, 17 PRs in 9 years 4 months
Contributions summary:Michael primarily worked on the USRP™ Hardware Driver Repository, specifically contributing to the low-level firmware and hardware aspects of the project. Their contributions involved fixing bugs related to double locks, invalid iterators, uninitialized variables, and missing breaks in switch statements. The user also marked unused parameters and corrected logical errors, demonstrating a strong understanding of low-level C++ and embedded systems programming principles.
driverusrphardwaresdruhd
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