Mihir Mahajan
Electrical Validation Engineer
Folsom, California, United States
Summary
👤
Senior🎓
Top SchoolMihir Mahajan is an Electrical Validation Engineer with eight years of hands-on experience in system and electrical validation for leading semiconductor firms including Intel and Solidigm. He holds an M.S. in Electrical and Electronics Engineering and has strong RTL/design-for-test skills across Verilog/VHDL, Synopsys toolflows, and transistor-level CMOS layout work from Cadence Virtuoso. Mihir combines embedded systems expertise—LabVIEW application development and multiple fieldbus protocols (RS232, USB, CAN, MODBUS, GPIB, I2C)—with practical test automation using Perl/TCL to accelerate verification cycles. He has delivered verification-driven designs (91%+ coverage on an asynchronous FIFO project) and built test harnesses that bridge lab instrumentation and DUTs. Comfortable leading both independent and collaborative efforts, he seeks roles in digital/ASIC design, design automation, or validation where his mix of lab, automation, and RTL experience adds immediate value. An often-overlooked strength is his background in GUI-driven test systems, enabling rapid deployment of reproducible test and debug environments for complex hardware.
9 years of coding experience
5 years of employment as a software developer
California State University, SacramentoBachelor of Engineering (BE) Instrumentation, Bachelor of Engineering (BE) Instrumentation at Bharati Vidyapeeth College of Engineering, Navi MumbaiDiploma Instrumentation, Diploma Instrumentation at V.P.M's polytechnic , ThaneSSC High School/Secondary Certificate Programs, SSC High School/Secondary Certificate Programs at I.E.S's G.N.V, Titwala
English, Marathi, Hindi
Github Skills (12)
fifo10
alu10
counter10
cadence-virtuoso9
asynchronous9
verilog9
fsm8
simulation8
vlsi8
multiplexer7
testbench7
pdf6
Programming languages (2)
Github contributions (5)
mihir8181/VerilogHDL-Codes
Feb 2019 - May 2019
Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
Contributions:72 commits, 65 pushes, 1 branch in 2 months
simulationtestbenchverilogverilog-projectverilog-code
mihir8181/Python-and-Machine-Learning
Jun 2019 - Aug 2019
Contributions:11 commits, 10 pushes, 1 branch in 1 month
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