Ming-yi Lai
Compiler Engineer at MediaTek
Taiwan
Summary
🤩
Rockstar🎓
Top SchoolMing-yi Lai is a compiler engineer and final-year master's student from Taiwan with two years of industry experience building RISC-V toolchains and system software. At MediaTek he implemented ISA extensions (Zicfilp/Zicfiss) across LLVM/Clang, LLD, musl, libunwind and the Spike simulator, co-developing psABI specs and upstreaming parts to open source. Previously at Synology he designed high-performance C++ systems, custom VFS filesystems, and cloud backends in Go, giving him a strong full-stack systems perspective. His open-source contributions to LLVM and the RISC-V ISA simulator demonstrate production-grade expertise in compiler backends, simulator cores, and security features like control-flow integrity and shadow stacks. He also brings applied ML systems experience from TVM/MLIR work during a MediaTek internship and distributed deep learning analysis at ITRI. Quietly pragmatic, he blends low-level ISA work with practical runtime and tooling improvements that ship in real products.
2 years of coding experience
2 years of employment as a software developer
Master's degree, Computer Science, Master's degree, Computer Science at 國立清華大學Bachelor of Engineering - BE, Computer Science, Bachelor of Engineering - BE, Computer Science at National Tsing Hua University
English, Chinese
Github Skills (12)
risc-v10
c-language10
exception-handling10
clangd10
cprogramming-language10
clang10
llvm10
compiler-development10
assemble9
assembler9
assembly9
elf8
Programming languages (4)
Github contributions (5)
llvm/llvm-project
Mar 2024 - Mar 2026
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
Role in this project:
Back-end Developer
Back-end DeveloperContributions:49 reviews, 27 PRs, 9 pushes in 2 years 1 month
Contributions summary:Ming-yi primarily contributed to the Clang compiler, specifically focusing on RISC-V target support and control-flow integrity (CFI) features. Their work included introducing new command-line options for RISC-V Zicfilp CFI, implementing preprocessor macros related to shadow stacks, and modifying code to support the use of shadow stacks. Additionally, they modified the `llvm-readobj` tool to dump the contents of the `.note.gnu.property` section. Furthermore, they refactored the `libunwind` to remove CET keywords.
compilerllvmtoolchain
riscv-software-src/riscv-isa-sim
Jan 2024 - Jul 2025
Spike, a RISC-V ISA Simulator
Role in this project:Back-end Developer
Back-end DeveloperContributions:27 reviews, 3 PRs, 40 comments in 1 year 5 months
Contributions summary:Ming-yi significantly contributed to the implementation of the Zicfilp extension within the RISC-V ISA simulator, `riscv-isa-sim`. Their work involved adding new instructions (`lpad`), integrating them into the disassembler, and implementing the corresponding behavior within the simulator's core execution logic. They also added new CSR fields and handled state management during traps and indirect jumps to support the Zicfilp extension, ensuring correct behavior within the simulated environment. The user demonstrated proficiency in modifying the core simulator files, including those related to instruction decoding, execution, and exception handling.
risc-v
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