Mitch Bailey
Technical Advisor at Shuhari System
Saga Metropolitan Area Japan
Summary
👤
Senior🎓
Top SchoolMitch Bailey is a technical advisor with over a decade of hands-on experience in semiconductor physical verification, specializing in pre-tapeout error detection for leading-edge memory and SoC designs. Based in Saga, Japan, he leverages open-source flows—most notably contributing backend work to the well-known OpenLane project—to automate RTL-to-GDSII flows and add electrical rule checks, LVS and spice/export enhancements. He has a long history of practical tooling: from developing full-chip leak detection and congested-channel routers to simplifying silicon compiler workflows into single-command operations. As a consultant for efabless he enabled device-level LVS for shuttle runs and built custom CVC-RV based checkers that prevent missing I/O connections. Mitch combines deep legacy experience dating back to Hitachi ULSI with modern open-source EDA integration, making him adept at bridging established tapeout practices with new, community-driven toolchains. An often-overlooked strength is his knack for translating niche verification checks into generalized, reusable tools that improve flow robustness across projects.
10 years of coding experience
25 years of employment as a software developer
The Ohio State University
Github Skills (8)
rt10
verilog10
asic10
tcl10
vlsi10
magick10
magicleap10
yosys8
Programming languages (11)
Github contributions (5)
The-OpenROAD-Project/OpenLane
Nov 2020 - Oct 2022
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Role in this project:
Backend Engineer
Backend EngineerContributions:1 review, 13 commits, 10 PRs in 1 year 11 months
Contributions summary:Mitch primarily focused on modifying the OpenLane flow, which involves automating RTL to GDSII. Their contributions include incorporating Circuit Validity Checker (CVC) for electrical rule checks and implementing GDS LVS (Layout Versus Schematic) capabilities. They also made changes related to spice export and DRC checks. The user also refactored CVC related code by renaming and translating it to be a more general ERC.
rtlfoundrymagicmethodologyvlsi
d-m-bailey/stic
Nov 2016 - Apr 2020
Contributions:27 pushes, 1 branch, 4 issues in 3 years 5 months
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