Mohamed Eldafrawy
Compiler Engineer at Groq
Ontario, Canada
Summary
🤩
Rockstar🎓
Top SchoolMohamed Eldafrawy is a Compiler Engineer with eight years of experience bridging FPGA architecture research and practical compiler/back-end engineering. Currently at Groq after a stint as a Deep Learning Acceleration Engineer at Intel, he blends academic rigor from a U of T MASc—where he explored FPGA architectural tweaks for neural network accelerators—with production-grade compiler work. He contributes to notable open-source FPGA CAD tooling (VTR/verilog-to-routing), driving refactors and architectural improvements that reveal a knack for clean, maintainable systems. Comfortable across hardware-software boundaries, he brings hands-on FPGA, NoC debugging, and deep-learning acceleration experience to optimize compiler and accelerator stacks.
8 years of coding experience
2 years of employment as a software developer
Bachelor of Applied Science - BASc, Electronics Engineering, 0.79 (Excellent with Highest Honors), Bachelor of Applied Science - BASc, Electronics Engineering, 0.79 (Excellent with Highest Honors) at The German University in CairoExchange Semester, Communications Circutis and Systems, 1.0, Exchange Semester, Communications Circutis and Systems, 1.0 at Ulm UniversityMaster's degree, Electrical and Computer Engineering, 4.0, Master's degree, Electrical and Computer Engineering, 4.0 at University of Toronto
English, German, Arabic
Stackoverflow
1reputation
0reached
0answers
0questions
Github Skills (12)
fpga10
verilog10
eda10
cad10
algorithms9
data-structure9
cprogramming-language9
c-language9
algorithm9
data-structures9
url-routing9
placement8
Programming languages (3)
Github contributions (5)
verilog-to-routing/vtr-verilog-to-routing
Feb 2019 - Jul 2020
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Role in this project:
Back-end Developer & Software Architect
Back-end Developer & Software ArchitectContributions:179 commits, 5 PRs, 96 pushes in 1 year 5 months
Contributions summary:Mohamed primarily contributed to the VTR-Verilog-to-Routing project by fixing bugs, improving code organization, and refactoring. Their work involved modifying the `t_pb` structure and associated functions, including the `hierarchical_type_name` method. The user also addressed compilation warnings, removed unnecessary whitespace and data structures, and implemented functionalities related to chain patterns. These changes suggest a focus on improving the underlying architecture and the functionality of the Verilog-to-routing tool.
vtrcadedaplacementsynthesis
MohamedEldafrawy/newRep
Mar 2018 - Mar 2018
Contributions:2 PRs, 5 pushes, 4 branches in 1 day
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