Mohamed Frikha
Emulation Tools Engineer
Aix-en-Provence, Provence-Alpes-Côte d'Azur, France
Summary
🤩
Rockstar🎓
Top SchoolMohamed Frikha is an Emulation Tools Engineer with three years of experience building HW+SW emulation environments for RISC-V SoCs, currently collaborating with analog, digital, architecture, and verification teams at SEALSQ. He has hands-on experience making the open-source CVA6 RISC-V core more configurable—contributing documentation and specification changes around MSTATUS, cache and interrupt behavior—which reflects a deep understanding of core internals beyond typical tooling work. Prior roles include developing Python-based data processing with Jinja templating and an industrial internship focused on RISC-V customization at Thales Silicon Security. Based in Aix-en-Provence, he combines systems-level architecture insight with practical implementation skills, bridging silicon design and software emulation to accelerate SoC validation.
3 years of coding experience
Baccalauréat général, Ingénierie électrique et électronique, Baccalauréat général, Ingénierie électrique et électronique at Ecole Nationale d'Ingénieurs de TunisGrenoble INP EsisarCycle préparatoire, Maths physiques (MP), Cycle préparatoire, Maths physiques (MP) at Esprit prépa
Github Skills (9)
cpu10
risc-v10
embedded10
asic10
registers10
sys10
systemverilog-hdl10
documentation9
fpga8
Programming languages (2)
Github contributions (4)
openhwgroup/cva6
Mar 2023 - Aug 2023
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Role in this project:
Embedded Systems Engineer / System Architect
Embedded Systems Engineer / System ArchitectContributions:2 reviews, 12 PRs, 6 comments in 4 months
Contributions summary:Mohamed primarily contributed to the project by modifying documentation and specifications related to the RISC-V CVA6 core. Their changes focused on adding and clarifying aspects of the MSTATUS register, including the addition of fields and legal values. They also addressed issues related to cache and interrupt configurations, demonstrating an understanding of the core's internal structure.
cpurisc-vasicbootingariane
frikhaAziz/cva6
Mar 2023 - Jun 2023
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Contributions:2 PRs, 4 pushes, 3 branches in 2 months
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