Mohamed Kassem
Cofounder & CEO at Daytona
San Francisco Bay Area United States
Summary
👤
Senior🎓
Top SchoolMohamed Kassem is a serial founder and veteran semiconductor executive with 10+ years in chip design and decades of analog/mixed-signal leadership spanning TI, Mentor Graphics, and startup ventures. As Cofounder & CEO of NativeChips.ai and Cofounder of ChipFoundry, he focuses on democratizing custom silicon—combining open-source methodologies, AI-native no-code flows, and new business models to collapse time and cost to silicon. He previously served as CTO & Cofounder of Efabless, helping pioneer community-driven, automated RTL-to-GDSII flows and enabling designers worldwide to ship real silicon. His technical chops include hands-on Verilog and VLSI toolchain contributions to prominent open-source projects like OpenLane/OpenROAD, reflecting deep familiarity with physical implementation and tapeout automation. Based in the Bay Area, he also advises and invests in early-stage AI-hardware and fabrication startups, bringing operator experience, product-to-manufacturing know-how, and a belief that open hardware will scale the next wave of device innovation. An interesting wrinkle: he blends enterprise platform-building with low-level silicon design, equally comfortable in boardroom strategy and editing Verilog for analog/digital modules.
10 years of coding experience
26 years of employment as a software developer
Bachelor of Engineering - BE Electronics and Communications Engineering, Bachelor of Engineering - BE Electronics and Communications Engineering at Ain Shams UniversityM.Sc. Electrical Engineering, M.Sc. Electrical Engineering at University of Waterloo
Github Skills (8)
yosys10
asic10
vlsi10
magick10
magicleap10
rt9
verilog9
system-on-chip8
Programming languages (3)
Github contributions (5)
The-OpenROAD-Project/OpenLane
Jul 2020 - Jul 2020
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Role in this project:
Embedded Systems Engineer / VLSI Engineer
Embedded Systems Engineer / VLSI EngineerContributions:10 commits in 6 days
Contributions summary:Mohamed made significant contributions to the OpenLane project, primarily focused on the design and implementation of hardware modules described in Verilog. The commits show the user adding and modifying Verilog code for components like the APU, square wave generators, and triangle wave generators, which are likely components of an ASIC design. They also made changes to scripting files for the Magic and OpenROAD tools, indicating involvement in the automated RTL to GDSII flow, which suggests knowledge of VLSI design tools and methodologies.
rtlfoundrymagicmethodologyvlsi
kassemmkk/openlane2-ci-designs
Mar 2025 - Mar 2025
Continuous Integration Designs for OpenLane 2.0.0 or higher
Contributions:3 PRs, 2 pushes, 1 branch in 1 day
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