Mohammad Ewais is an ML/HPC architect and PhD candidate in Computer Engineering at the University of Toronto with eight years of experience spanning ASIC/FPGA design, compiler development, and datacenter memory research. At AMD he architects datacenter GPUs and models new features end-to-end—creating workloads, simulator-based proofs of concept, and ROI analyses that bridge silicon constraints and ML performance needs. His doctoral work focuses on disaggregated memory hierarchies, having built a large-scale distributed architecture simulator to quantify network and memory tradeoffs and plan open-source release. Earlier roles include LLVM backend and Virtual ISA design at Huawei and FPGA virtualization/orchestration for Kubernetes at U of T, showing a rare mix of low-level hardware design, compiler toolchain expertise, and cloud-native deployment. He brings practical production instincts from silicon and toolchain projects together with deep research experience in memory systems and cache compression, often implementing simulators and prototypes from scratch. Based in Toronto, he combines academic rigor with industry delivery to drive architecture features that measurably improve ML datacenter efficiency.
8 years of coding experience
4 years of employment as a software developer
Bachelor's degree, Electronics and Communications Engineering, Bachelor's degree, Electronics and Communications Engineering at Alexandria University
Master of Applied Science, Computer Engineering, Master of Applied Science, Computer Engineering at The University of British Columbia
Doctor of Philosophy - PhD, Computer Engineering, Doctor of Philosophy - PhD, Computer Engineering at University of Toronto
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