Moritz Schneider
Senior Incident Response Analyst at Thomson Reuters
Zurich, Zurich, Switzerland
Summary
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Rockstar🎓
Top SchoolMoritz Schneider is a Senior Incident Response Analyst based in Zurich with 11 years of experience bridging digital forensics, threat response and applied research. He has progressed from research roles at ZHAW to senior forensic and incident roles at EY and now leads incident response at Thomson Reuters, combining rigorous investigative discipline with practical remediation. His technical background spans embedded systems and IoT—evidenced by contributions to the openhwgroup/cva6 RISC‑V core where he implemented SPI/SD card peripherals and bootrom improvements for FPGA targets—bringing low-level systems insight to enterprise security incidents. Moritz holds an MSc in Information Systems and a multi-disciplinary foundation in business IT, enabling him to translate technical findings into audit-ready, business-focused outcomes. Colleagues know him for methodical incident handling and a knack for uncovering non-obvious system-level causes that accelerate root-cause analysis. He balances hands-on technical contributions with clear communication to stakeholders across legal, compliance and engineering teams.
10 years of coding experience
3 years of employment as a software developer
Bachelor of Science (BSc), Business Information Technology, Bachelor of Science (BSc), Business Information Technology at School of Management and Law, ZHAWMaster of Science (MSc), Information Systems, Master of Science (MSc), Information Systems at Universität ZürichBachelor's degree, Business Information Technology, Bachelor's degree, Business Information Technology at City University of New York-Baruch CollegeInformatiker EFZ Schwerpunkt Applikationsentwickler, Informatiker EFZ Schwerpunkt Applikationsentwickler at Kantonsschule Büelrain, Winterthur
German, English, French
Github Skills (10)
fpga10
risc-v10
spi10
systemverilog-hdl10
bootloader9
asic8
cpu8
ria8
aria28
ane8
Programming languages (9)
Github contributions (5)
openhwgroup/cva6
Oct 2018 - Jul 2022
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Role in this project:
Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:3 reviews, 33 commits, 29 PRs in 3 years 9 months
Contributions summary:Moritz's contributions primarily revolve around the addition and modification of peripherals within the CVA6 RISC-V CPU core, focusing on FPGA implementation. Their work includes integrating an SD card in SPI mode, connecting the SPI interrupt to the PLIC, and updating the SPI peripheral. Further contributions involve modifying the bootrom, including improvements to error reporting and increasing ROM size.
cpurisc-vasicbootingariane
Moschn/ariane
Aug 2018 - Oct 2024
Contributions:94 pushes, 25 branches in 6 years 3 months
risc-vcpuriscvarianestudio
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