Mridul Verma is a Senior Lead Engineer with 13 years of hands-on experience in static timing analysis and physical design, currently driving GPU STA at Qualcomm. He has led timing-constraint development and signoff across multiple SoCs at NXP and supported complex timing closure for clients at Synopsys using PrimeTime and advanced flows like PT-ECO, DMSA, SMVA, AOCV/POCV and hypertrace modes. Mridul brings practical layout familiarity across leading nodes (TSMC N5/N6/N7/16/22, Samsung 8LPP/4) and automates flows with TCL, Perl and cshell to accelerate signoff cycles. Known for bridging application engineering and physical design, he pairs deep tool expertise with on-the-ground constraint strategy to resolve multi-scenario, multi-voltage timing challenges. Based in Noida, he combines IP-level rigor with production-driven pragmatism, often surfacing subtle variation and cross-corner issues before tapeout.
13 years of coding experience
5 years of employment as a software developer
Bachelor of Technology (B.Tech.) Electronics and Communications Engineering, Bachelor of Technology (B.Tech.) Electronics and Communications Engineering at ABES Engineering College
Higher secondary examination PCM+Computer science, Higher secondary examination PCM+Computer science at Brij Bhushan Lal public school, Bareilly
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Mridul Verma - Senior Lead Engineer (GPU STA) at Qualcomm