Mustafa Abbas
San Francisco Bay Area United States
Summary
🤩
Rockstar🎓
Top SchoolMustafa Abbas is a hardware-focused software engineer with nine years of experience specializing in spatial and reconfigurable hardware design and their applications in high-performance computing. Based in the San Francisco Bay Area, he combines graduate-level training from the University of Toronto with practical CAD tooling work, contributing backend improvements to the widely used open-source VTR (Verilog-to-Routing) flow. His contributions to rr_graph generation—adding clearer pin naming and nuanced clock-pin handling—reflect a detail-oriented approach to tooling that improves FPGA research productivity. Mustafa blends systems-level thinking with hands-on code changes, making him effective at bridging hardware architecture concepts and software implementation.
9 years of coding experience
Bachelor’s Degree, Bachelor’s Degree at Bucknell UniversityMaster’s Degree, Master’s Degree at University of Toronto
Japanese, Arabic, English
Github Skills (7)
fpga10
url-routing10
verilog10
c-language10
cprogramming-language10
eda9
cad9
Programming languages (4)
Github contributions (4)
verilog-to-routing/vtr-verilog-to-routing
Apr 2018 - Apr 2020
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Role in this project:
Back-end Developer
Back-end DeveloperContributions:151 commits, 9 PRs, 161 pushes in 2 years
Contributions summary:Mustafa primarily worked on improving the routing resource graph generation process within the VTR-Verilog-to-Routing repository. Their contributions focused on enhancing the printing of verbose information during the generation of the routing resource graph (rr_graph), specifically by adding pin names to the output and making adjustments to the handling of clock pins. This involved modifying existing code within the vpr module to incorporate options for clock handling and adjusting the cost index for segments. Furthermore, the user added functions to handle clock pins.
cadfpgaverilogvtrplacement
mustafabbas/lid_for_fpgas
Sep 2019 - Oct 2019
Parameterizable latency insensitive Design Styles for FPGAs
Contributions:3 commits, 2 PRs, 1 push in 12 days
fpgasinsensitivelatencystylesfpga
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