Summary
Muzaffer Kal is a Principal Silicon Engineer with over a decade of experience architecting custom SoCs and accelerators for computer vision and machine learning, spanning ASIC and FPGA implementations. He leads cross-functional teams through RTL-to-GDSII flows at advanced nodes, combining Verilog/SystemVerilog expertise with Python DSLs, UVM verification, and full back-end implementation including timing, CTS, LVS and DRC. Muzaffer has driven novel ML arithmetic standardization work (including FP8 and new 752 efforts) and has shipped CIM/IMC accelerator blocks and RISC-V co-designed systems that push power and efficiency boundaries. His background in sensor integration and low-power VIO systems gives him uncommon depth across mixed-signal, memory, and algorithm-hardening for embedded inference. Currently shaping next-generation MAIA AI accelerator architecture, he blends hands-on RTL design with systems-level product thinking to deliver silicon that materially improves ML compute density.
10 years of coding experience
10 years of employment as a software developer
BS EE, BS EE at Boğaziçi University