RTL Design And FPGA Engineer at Elecment Design Fab
Noida, Uttar Pradesh, India
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Summary
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Senior
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Top School
Naman Chauhan is an RTL Design and FPGA engineer with eight years of hands-on experience in Verilog, SystemVerilog, and testbench-driven verification, currently contributing at Elecment Design Fab. He blends practical embedded prototyping—evident from an IoT self-balancing bike project and Arduino/ESP8266 work—with formal RTL design skills to bridge hardware and firmware development. His background includes focused roles and internships across VLSI training and startups, giving him exposure to both design flows and verification methodologies. Known for clear communication and analytical rigor, he enjoys pushing code in C++ and Python while exploring fast-paced prototyping with FastAPI-based tools.
8 years of coding experience
Bachelor of Technology - BTech, Bachelor of Technology - BTech at Raj Kumar Goel Institute of Technology, Ghaziabad
Bachelor of Technology - BTech, Electronics and Communications Engineering, Bachelor of Technology - BTech, Electronics and Communications Engineering at Dr. A.P.J. Abdul Kalam Technical University
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