Naums Mogers is a senior software engineer and PhD researcher specializing in compiler optimizations for deep neural networks and heterogeneous hardware, currently advancing custom kernel infrastructure for Google TPUs. With 11 years of experience spanning research internships at Microsoft Research and Arm to production compiler work at Google, he blends academic rigor (PhD at Edinburgh, Lift group) with hands-on systems engineering across ML frameworks and GPUs/TPUs. His background includes extending functional data-parallel compilers to target accelerators, generating HDL for hardware synthesis, and practical contributions to Caffe and TensorFlow pipelines. He has a track record of cross-disciplinary projects—from FPGA and microcontroller prototypes to antivirus engine development—reflecting a rare mix of low-level systems, hardware-aware compilation, and applied ML. Notably, his work on MLIR-based Mosaic/Pallas for sparse block-centric TPU kernels earned recognition for measurable efficiency gains.
11 years of coding experience
9 years of employment as a software developer
Doctor of Philosophy - PhD Optimising Compilation of Machine Learning Models for Heterogeneous Hardware, Doctor of Philosophy - PhD Optimising Compilation of Machine Learning Models for Heterogeneous Hardware at The University of Edinburgh
Secondary Education, Secondary Education at Riga School No 40
Bachelor's Degree Computer Science (with a year in industry), Bachelor's Degree Computer Science (with a year in industry) at University of York
Computer Science, Computer Science at Progmeistars Programming School
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