Neel Gala
CTO Co-Founder at InCore Semiconductors Pvt. Ltd.
Chennai, Tamil Nadu, India
Summary
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Rockstar🎓
Top SchoolNeel Gala is a CTO and co-founder with a decade of experience building silicon-proven RISC-V processors and SoC IP, leading InCore Semiconductors from concept to high-volume ASIC delivery. He combines deep academic roots—a PhD focused on approximate computing and low-power/nano-oscillator architectures—with hands-on system design and verification experience from IIT Madras and the SHAKTI microprocessor program. A pragmatic engineering leader, Neel has driven MMU and core designs, built secure microcontrollers, and forged foundry partnerships across process nodes. He is also an active open-source contributor to key RISC-V projects (arch-test, Spike, riscv-opcodes), improving simulator integration, test automation, and opcode code generation formats. Notably, his research work on stochastic checkers and tunable approximate circuits has translated into practical IP optimizations that reduce area and power while preserving application quality. Based in Chennai, he blends academic rigor with startup execution to commercialize advanced processor IP for fault-tolerant, security and AI/ML verticals.
9 years of coding experience
1 year of employment as a software developer
Indian Institute of Technology MadrasB.Tech Electronics and Communications Engineering, B.Tech Electronics and Communications Engineering at National Institute of Technology Warangal
Stackoverflow
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Github Skills (32)
simulation10
assembly10
c-language10
python10
simulator10
simulations10
risc-v10
makefile10
code-generation10
parsing10
assemble10
assembler10
test-suite10
text-parsing10
cprogramming-language10
Programming languages (11)
Github contributions (5)
riscv-non-isa/riscv-arch-test
Nov 2018 - Dec 2022
Role in this project:
Back-end Developer, Test Automation Engineer
Back-end Developer, Test Automation EngineerContributions:2 releases, 32 reviews, 147 commits in 4 years 2 months
Contributions summary:Neel primarily contributed to the `riscv-arch-test` repository by modifying and adding tests related to the RISC-V instruction set architecture. Their work involved fixing issues related to trap handling, spike signature formats, and the addition of tests for various instructions, including those in the K and D extensions. Furthermore, the user restructured the test suite, indicating a focus on test organization and maintainability. They also added post-processing scripts for signature generation and verification using different simulators.
riscv/riscv-opcodes
Apr 2022 - Jan 2023
RISC-V Opcodes
Role in this project:Back-end Developer
Back-end DeveloperContributions:21 reviews, 52 commits, 16 PRs in 9 months
Contributions summary:Neel primarily contributed to the project by modifying the Python scripts related to parsing and generating code for RISC-V opcodes. Their work included adding support for new code generation formats like SpinalHDL, Go, and improving the existing LaTeX table generation. They also focused on improving the overall structure and functionality of the parsing scripts, enhancing logging for better readability and ensuring the correct handling of pseudo instructions.
risc-vriscopcodesfpga
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