Neil Katahira is a Design Verification Engineer based in San Jose with 10 years of experience specializing in digital verification for large-scale ADAS and IVI systems. At Texas Instruments he led DV efforts for an ADAS quad-lane FPD-Link IV deserializer hub, supervising a team of engineers and coordinating cross-functional validation and customer debug. He brings hands-on lab validation experience and RTL/gate-level verification across interfaces like I2C, CSI2 (CPHY/DPHY), PLL, BIST and eFuse, using Cadence tools such as Xcelium and Vmanager. His background in computer engineering from UC Davis is complemented by embedded-systems research building AI-enabled sensing kits and power-management firmware for precision agriculture. Known for turning complex hardware requirements into practical verification plans, he balances leadership with deep technical execution in both simulation and lab environments. Notably, he bridges system-level autonomy work from academia with high-volume consumer electronics verification in industry.
10 years of coding experience
Bachelor of Science - BS, Computer Engineering, Bachelor of Science - BS, Computer Engineering at University of California, Davis
Contributions:24 commits, 22 pushes, 1 branch in 20 days
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