Niansong Zhang is a research-focused hardware engineer and ECE PhD student at Cornell with eight years of experience building compiler toolchains, domain-specific languages, and hardware accelerators. He currently contributes to the Evolvable Distributed Accelerators project via SRC and has interned in research roles at NVIDIA, AMD, and Intel Labs, blending academic rigor with industry-grade systems. His work spans intelligent memory/storage architectures, NAS and model compression, and FPGA placement for systolic arrays—resulting in publications and a production-ready RapidLayout placement framework. Comfortable moving between compilers and hardware, he has repeatedly delivered DSL and compiler support that bridges algorithmic ML advances with efficient hardware realization. Based in Ithaca, he brings a rare combination of hands-on intern experience at leading chip companies and deep research expertise in EDA and accelerator co-design.
8 years of coding experience
2 years of employment as a software developer
MS/PhD, Computer Hardware Engineering, MS/PhD, Computer Hardware Engineering at Cornell University
Bachelor of Engineering - BE, Telecommunications Engineering, Bachelor of Engineering - BE, Telecommunications Engineering at Sun Yat-Sen University
Contributions:61 commits, 2 pushes, 1 branch in 10 months
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.
Request Free Trial
Niansong Zhang - Research Scholar at SRC Research Scholars Program