Summary
Nicholas Giamblanco is a Senior Member of Technical Staff with ~10 years of experience specializing in compiler technology, MLIR, and LLVM to bridge software and custom hardware for high-performance systems. He has led compiler and code-generation efforts across AI accelerators and memory-compute RISCV devices, delivering optimizations that materially accelerate simulation and verification (reported speed-ups up to ~76x and bug-discovery acceleration). Comfortable across ISAs (RISC-V, MIPS, ARM, custom) and fluent in hardware design languages like SystemVerilog, he uniquely combines compiler engineering with HLS and RTL co-simulation to shrink design cycles. Nicholas has shipped production compiler backends and custom tooling for wafer-scale and edge AI platforms while mentoring engineers and shaping cross-disciplinary teams. Beyond pragmatic delivery, he has a track record of turning research prototypes into deployable infrastructure and contributing novel approaches to static analysis and event-driven serialization for hardware. Based in Coquitlam, Canada, he holds an M.A.Sc. in Computer Engineering and thrives on squeezing more performance out of the entire hardware-software stack.
10 years of coding experience
8 years of employment as a software developer
Master of Applied Science (M.A.Sc.) Computer Engineering, Master of Applied Science (M.A.Sc.) Computer Engineering at University of Toronto
Toronto Metropolitan University
English, French