Nico Engelhardt
CEO at YosysHQ
Vienna, Austria
Summary
🤩
Rockstar🎓
Top SchoolNico Engelhardt is a CEO and researcher with 12 years of experience making FPGAs accessible as practical computing platforms, blending deep academic work with hands-on open-source engineering. He led the GraVF project during his PhD to automate distributed graph processing across multi-FPGA systems and now directs YosysHQ while contributing backend fixes and features to the widely used Yosys synthesis suite. His background spans verification, EDIF support, and test automation for RISC-V cores, reflecting a rare combination of hardware-software co-design and toolchain expertise. Based in Vienna, he has a track record of turning complex synthesis and verification problems into usable tooling and has a knack for improving obscure backend behaviors (e.g., macOS command fixes and scratchpad scripting) that materially boost developer productivity.
12 years of coding experience
1 year of employment as a software developer
Master of Science (M.Sc.), Computer Science, Master of Science (M.Sc.), Computer Science at École Normale Supérieure de Cachan Antenne de BretagneThe University of Hong Kong (HKU)Master of Science (M.Sc.), Computer Science, Master of Science (M.Sc.), Computer Science at IFSIC
English, French, German, Japanese
Github Skills (29)
verilog10
systemverilog10
back-end-development10
python10
scripting10
cpu10
risc-v10
yosys10
verification10
verilator10
automation10
script10
sh10
automations10
shell10
Programming languages (13)
Github contributions (5)
m-labs/migen
Jul 2013 - Oct 2018
A Python toolbox for building complex digital hardware
Role in this project:
Embedded Systems Engineer / Automation Engineer
Embedded Systems Engineer / Automation EngineerContributions:8 commits, 4 PRs, 5 comments in 5 years 3 months
Contributions summary:Nico focused on adding and refining EDIF (Electronic Design Interchange Format) support within the migen framework. This involved implementing back-end functionality for EDIF conversion and adjusting code to work seamlessly with mibuild. The contributions included adding support for INOUT signals, adjusting build routines, and fixing memory simulation behavior to match generated verilog.
asicpythonvhdltoolboxsynthesis
YosysHQ/yosys
Jul 2019 - Jan 2023
Yosys Open SYnthesis Suite
Role in this project:Backend Developer
Backend DeveloperContributions:68 reviews, 98 commits, 200 PRs in 3 years 6 months
Contributions summary:Nico contributed to the Yosys Open SYnthesis Suite by addressing issues related to system synthesis, specifically focusing on the backend functionality. Their commits involved handling failures in system calls, fixing the show command for macOS, and integrating memory optimization steps before digital signal processing (DSP) mapping. Furthermore, the user added a command to read and modify scratchpad contents for customizing abc scripts.
synthesispythonsuiteyosys
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