Nils Wistoff
Researcher at RISC-V International
Zurich, Zurich, Switzerland
Summary
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Rockstar🎓
Top SchoolNils Wistoff is a researcher and hardware-focused embedded systems engineer with 8 years of experience designing digital architectures, tape-out workflows, and system-level integrations from Zurich. At PULP Platform he works on cutting-edge RISC-V accelerators and has contributed to notable open-source projects like CORE-V CVA6 and PULP Ara, adding peripherals, cache integrations, and automation for simulation flows. He combines academic rigor (PhD candidate at ETH Zürich and visiting fellow at UNSW) with practical industry experience from HENSOLDT, bringing a track record of making complex hardware-software boundaries work reliably. As Vice‑Chair of RISC-V International’s Timing Fences Task Group he helps shape standards-level timing and synchronization mechanisms, reflecting influence beyond individual projects. Colleagues know him for tackling low-level corner cases—such as RVI return fixes and semaphore-backed load/store tracking—that reveal a knack for making subtle, system-critical improvements.
8 years of coding experience
Indian Institute of Technology MadrasM.Sc., Computer Engineering, M.Sc., Computer Engineering at RWTH Aachen UniversityDoctor of Philosophy - PhD, Doctor of Philosophy - PhD at ETH ZürichUniversity Entrance Qualification (Abitur), University Entrance Qualification (Abitur) at German Embassy School Beijing, China
German, English, Chinese, French, Spanish
Stackoverflow
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Github Skills (12)
fpga10
hardware-designs10
risc-v10
cpu10
asic10
systemverilog10
systemverilog-hdl10
automation9
vector9
vector-math9
automations9
system-design8
Programming languages (11)
Github contributions (5)
openhwgroup/cva6
Aug 2019 - Jan 2023
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Role in this project:
Embedded Systems Engineer / Automation Engineer
Embedded Systems Engineer / Automation EngineerContributions:48 reviews, 59 commits, 85 PRs in 3 years 5 months
Contributions summary:Nils's contributions primarily involve modifications to the CVA6 core, which is a RISC-V CPU. They fixed conditions for the RVI return and added an APB timer peripheral, indicating a focus on hardware integration. Furthermore, the user's commits include modifying files related to simulation flow, which suggest they are involved with automated testing and build processes. Their work demonstrates an understanding of system-level design and integration within a hardware development context.
cpurisc-vasicbootingariane
pulp-platform/ara
Dec 2020 - Dec 2022
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
Role in this project:Embedded Systems Engineer
Embedded Systems EngineerContributions:36 commits, 1 PR, 61 pushes in 2 years
Contributions summary:Nils Wistoff's contributions primarily involve modifying and integrating components within the PULP Ara's hardware architecture. His work includes integrating an L2 cache into the test harness, adding a CSR (Control and Status Register) to toggle consistent mode for the accelerator, and adding support for line invalidations in the write-through cache. He also implemented load/store tracking mechanisms with semaphores. These modifications suggest a focus on hardware-level integration and optimization.
cpurisc-vasic64-bitcoprocessor
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