Niraj Menon
Senior Instructional Lab Coordinator
West Lafayette, Indiana, United States
Summary
👤
Senior🎓
Top SchoolNiraj Menon is a Senior Instructional Lab Coordinator and educator with 11 years of hands-on experience building lab curricula and tooling for computer engineering at Purdue University. He blends hardware design (SystemVerilog, RISC-V) and embedded systems with web development and DevOps to create practical learning platforms—reintroducing student-driven embedded projects and designing a custom RP2350-based development platform. Niraj has a track record of shipping automation and authoring custom autograding, simulation, and proctoring tools that let students work reliably both in and out of lab. He also taught SystemVerilog for Purdue’s STARS tape-out program, delivering an open-source flow that accelerates student prototyping. Known for reverse-engineering unknown hardware and building no-frills, student-friendly tools (including publicly hosted simulators), he pairs deep technical craft with a focus on scalable education.
11 years of coding experience
Master of Science in Electrical and Computer Engineering, Computer Engineering, Master of Science in Electrical and Computer Engineering, Computer Engineering at Purdue UniversityHigh School Diploma, HIGH SCHOOL/SECONDARY DIPLOMAS AND CERTIFICATES, ISC: 93%, ICSE: 90%, High School Diploma, HIGH SCHOOL/SECONDARY DIPLOMAS AND CERTIFICATES, ISC: 93%, ICSE: 90% at GEMS Modern Academy
English, Hindi, Malayalam
Github Skills (63)
verilog10
simulator9
simulation9
platformio9
debugging9
python9
yosys9
micropython9
stdin9
nodejs9
cmsis9
verilator9
stdout9
cpp9
fpga9
Programming languages (8)
Github contributions (5)
ece362-purdue/proton-labs
Dec 2024 - May 2026
Purdue Proton Lab Experiments for ECE 362
Contributions:165 pushes, 1 branch in 1 year 4 months
norandomtechie/ece270-simulator
Jun 2020 - Aug 2025
Source code for Web-Based Verilog Simulation Platform in ECE 27000 at Purdue University
Contributions:3 releases, 5 reviews, 11 PRs in 5 years 3 months
simulationverilogccssfpga
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