Noureddine Asni
Summary
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SeniorNoureddine Said is a Staff Embedded Software Engineer at SiFive with nine years of experience building bare-metal system software for RISC-V cores and SoCs. He combines a strong hardware/software co-design background with academic rigor from a PhD in Nanoelectronics, where he researched approximate and variable floating-point precision for CPU architectures. At Grenoble he developed one of France’s first practical RISC-V HW/SW training programs for engineering students, translating research platforms into hands-on curricula. Comfortable across toolchains from GCC and Spike to Verilator, he focuses on low-level firmware, multi-core bootstrapping, and driver integration for open-source CPU IP. Based in France, he blends production engineering at SiFive with teaching and published research, making him equally effective at shipping silicon-facing software and mentoring the next generation of embedded engineers.
9 years of coding experience
Github Skills (52)
chisel10
rocket-chip10
scala9
fpga8
risc-v8
gnu-toolchain8
electron7
typescript7
kernel7
asic7
cpu6
proxy6
yocto6
openembedded5
floating-point5
Programming languages (13)
Github contributions (5)
noureddine-as/cva6
Mar 2021 - Mar 2025
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Contributions:10 pushes, 5 branches in 4 years
linuxrisc-v
noureddine-as/zephyr
Sep 2019 - Mar 2023
Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.
Contributions:8 pushes, 2 branches in 3 years 6 months
architecturesscalablegit-repositorysecuresoftware-defined-radio
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