Oleg Petelin
Member Of Technical Staff at Cerebras Systems
Old Toronto, Ontario, Canada
Summary
🤩
Rockstar🎓
Top SchoolOleg Petelin is a Member of Technical Staff with 13 years of engineering experience spanning FPGA architecture, SoC and deep learning systems, and embedded software. He holds an MASc from the University of Toronto where he developed novel CAD tools and Wotan for analytic FPGA routing evaluation, and has applied those skills at Intel, Untether AI and Cerebras Systems. Proficient in C/C++, Verilog/VHDL, mixed-signal PCB design (Altium), Python and MATLAB, he blends low-level hardware design with software-driven CAD and ML workflows. An active contributor to the VTR open-source FPGA CAD flow, he’s improved routing features and metrics to tackle pathological connection cases. Comfortable moving between research and production, he brings a practical knack for turning architectural ideas into testable tooling and silicon-ready implementations.
13 years of coding experience
10 years of employment as a software developer
M.A.Sc., Electrical and Computer Engineering, M.A.Sc., Electrical and Computer Engineering at University of TorontoUndergraduate, Electrical Engineering, Undergraduate, Electrical Engineering at University of Waterloo
English, Russian
Github Skills (13)
fpga10
url-routing10
verilog10
eda10
cad10
data-structure9
cprogramming-language9
c119
c-language9
c179
data-structures9
algorithm9
algorithms9
Programming languages (1)
Github contributions (3)
verilog-to-routing/vtr-verilog-to-routing
May 2013 - May 2017
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Role in this project:
Back-end Developer
Back-end DeveloperContributions:108 commits, 37 pushes, 2 branches in 4 years
Contributions summary:Oleg contributed to the implementation of features related to routing in the VTR-Verilog-to-Routing repository, an open-source CAD flow for FPGA research. Their work involved adding functionality to perturb bidirectional output pins, specifically addressing pathological cases. The user also added and refactored code to add metrics for connection block evaluation.
vtrcadedaplacementsynthesis
opetelin/olegs_test_repo
Oct 2016 - Jan 2017
Contributions:8 pushes, 1 branch in 2 months
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