Oliver Vecchini is a Senior SoC Performance Engineer at Arm with a decade of experience modelling and optimising CPU and memory systems for real-world workloads. Educated with an MEng in Mathematical Computation (First Class, Dean's List, Outstanding Dissertation) from UCL, he has progressed from intern to senior engineer driving memory-system performance for next-generation Cortex designs. His work blends microarchitectural modelling, cycle-accurate C++ simulation, and coherent interconnect/memory-controller analysis to translate architectural ideas into measurable silicon-class performance. Based in Cambridge, he pairs rigorous mathematical training with practical engineering delivery, and is comfortable spanning low-level simulator development to full-system workload correlation. A less obvious strength is his consistent focus on building traffic-generation and coherence-correlation tools that make complex memory behaviours observable and testable.
10 years of coding experience
3 years of employment as a software developer
High School Diploma, High School Diploma at St Paul's School
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