Olof Kindgren
Senior Digital Design Engineer at Qamcom
Karlstad, Sweden
Summary
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Rockstar🎓
Top SchoolOlof Kindgren is a senior digital design engineer with 12+ years designing and verifying FPGA, ASIC and embedded software across consumer, automotive, military, telecom and research domains at Qamcom. He co-founded and directs the FOSSi Foundation and is the lead developer of widely used open-source silicon tooling such as FuseSoC and the SERV RISC‑V core, blending hands‑on RTL, verification and automation expertise with community building. His work spans SoC architecture, high‑speed interface design and verification strategies, and he frequently ties in high‑level software, UX and agile practices to streamline hardware development. An active contributor to prominent projects like PicoRV32 and Yosys-adjacent tooling, he focuses on practical tool integration (edalize, FuseSoC) that accelerates chip development and reproducible builds. Based in Karlstad, Sweden, he organizes and speaks at conferences and champions vendor‑neutral, open collaboration to push open‑source silicon forward.
12 years of coding experience
1 year of employment as a software developer
Computer engineering, Computer engineering at Linköping UniversityM.Sc.EE, Integrated Electronic System Design, M.Sc.EE, Integrated Electronic System Design at Chalmers University of Technology
Swedish, English, German, Spanish
Stackoverflow
1reputation
0reached
1answer
0questions
Github Skills (50)
verilog10
systemverilog10
python10
testing10
axi410
memory-management10
risc-v10
yosys10
build-system10
makefile10
vhdl10
verilator10
testbed10
automation10
digital-design10
Programming languages (27)
Github contributions (5)
olofk/serv
Oct 2018 - Dec 2022
SERV - The SErial RISC-V CPU
Role in this project:
Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:4 releases, 10 reviews, 328 commits in 4 years 2 months
Contributions summary:Olof contributed to the development of the SERV processor by implementing and modifying instructions, including jal, addi, lui, and lb. The code changes involve modifications to the top-level RTL and the decode and memory interface modules, with a focus on implementing new instructions and improving the core's functionality. These changes include implementing branch, store, and load instructions, which are fundamental building blocks for a functioning processor.
risc-vcpuasicserialriscv
olofk/edalize
Oct 2018 - Jan 2023
An abstraction library for interfacing EDA tools
Role in this project:Back-end Developer & Test Automation Engineer
Back-end Developer & Test Automation EngineerContributions:5 releases, 89 reviews, 174 commits in 4 years 3 months
Contributions summary:Olof primarily contributed to the project by implementing core features and functionalities, as evidenced by the commit messages referencing release versions and loading EDA APIs. They also significantly contributed to testing by creating, modifying, and extending existing test cases and integrating test hooks. Furthermore, the user added support for tools like yosys and nextpnr in the existing framework.
vivadovhdlxilinxsystemverilogsynthesis
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