Summary
Osaze Shears is an FPGA and ASIC-focused design engineer with 12 years of experience building and verifying complex SoCs, high-throughput hardware accelerators, and prototyping platforms across industry and research. He has driven SystemVerilog/ UVM verification, HLS accelerator implementations, and top-level SoC integration for projects ranging from homomorphic-encryption ASICs to heterogenous FPGA-GPU object-tracking systems. Currently at Reliable Robotics after a senior engineering role at USC ISI and graduate research at Virginia Tech’s MICS lab, he blends hands-on FPGA toolchain automation with low-power neuromorphic and spiking neural network research. An experienced mentor and tutor, Osaze has spent years teaching and guiding students while also collaborating on emulation and production validation efforts like HAPS and VCU/VCU128 platforms. Based in Mountain View, he pairs deep hardware verification expertise with a practical focus on secure supply-chain and runtime considerations that often go unnoticed in design work.
12 years of coding experience
7 years of employment as a software developer
Master of Science - MS Computer Engineering, Master of Science - MS Computer Engineering at Virginia Tech
Bachelor's degree Computer Engineering, Bachelor's degree Computer Engineering at George Mason University
High School Diploma Technology, High School Diploma Technology at Appomattox Regional Governor's School
English