Øystein Knauserud
Staff Design Engineer at Silicon Labs
Lena, Norway
Summary
🤩
Rockstar🎓
Top SchoolØystein Knauserud is a Staff Design Engineer with six years of recent focused experience in digital design, FPGA and ASIC development, currently at Silicon Labs. He brings a deeper hardware-verification and debug pedigree from contributions to notable open-source RISC-V projects (CV32E40P and CORE-V verification), where he improved SystemVerilog RTL, tracer/debug trigger integration, and assembly-level debug tests. Prior roles span senior FPGA design in ultrasound NDT at DolphiTech and hardware engineering at ARM Norway, giving him broad system-level and silicon-focused expertise. He blends hands-on RTL development with test automation and verification, ensuring alignment between RTL and simulation models. Based in Lena, Norway, he pairs a formal MSc in Electronics from NTNU with a practical track record of shipping complex hardware features. Colleagues value his knack for surfacing subtle debug issues that improve observability and correctness in CPU cores.
5 years of coding experience
6 years of employment as a software developer
Stange VGSNorwegian University of Science and Technology
Github Skills (18)
debugging10
debug10
assembly10
systemverilog10
uvm10
risc-v10
verification10
vhdl10
sys10
assemble10
assembler10
hdl10
embedded10
cpu9
cpu-architecture9
Programming languages (5)
Github contributions (5)
openhwgroup/core-v-verif
Aug 2020 - Dec 2022
Functional verification project for the CORE-V family of RISC-V cores.
Role in this project:
Backend Developer & Test Automation Engineer
Backend Developer & Test Automation EngineerContributions:57 reviews, 113 commits, 40 PRs in 2 years 4 months
Contributions summary:Øystein contributed to the functional verification of RISC-V cores within the CORE-V family. Their work involved adding and modifying assembly-level tests related to debug functionality, including ebreak handling, single-stepping, and trigger mechanisms. The user's commits demonstrate a focus on testing and verifying the correct operation of hardware debug features, likely using SystemVerilog and UVM-based methodologies.
risc-vsystemverilogriscverificationcores
openhwgroup/cv32e40p
Sep 2020 - Nov 2020
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Role in this project:Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:5 reviews, 5 commits, 2 PRs in 1 month
Contributions summary:Øystein primarily contributed to the development and debugging of the CV32E40P RISC-V CPU core. Their work focused on enhancing the hardware description language (HDL) implementation, specifically addressing issues related to instruction retirement, sleep/wake-up cycles, and debug triggers. The user integrated trigger matching into the tracer and debug mechanisms to ensure accurate execution and alignment between RTL and other simulation models, highlighting a focus on SystemVerilog code improvements.
risc-vcpupulpuvmriscv
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