Pablo Camacho
Founder & FPGA Team Lead at Citrobits GmbH
Bavaria, Germany
Summary
👤
Senior🎓
Top SchoolPablo Camacho is a founder and FPGA team lead with 11 years of experience designing high-speed digital signal processing systems for telecommunications and software-defined radio. He combines deep theoretical DSP knowledge with hands-on expertise in VHDL/Verilog, fixed-point modelling, high-speed transceiver design and Linux kernel driver development to deliver PHY-layer implementations and FPGA-software co-processing at multi-gigabit bandwidths. As founder of Citrobits and former contractor for Huawei and AED Engineering, he has taken prototypes from algorithmic modelling through RF characterization and production-grade interfaces. Pablo’s uncommon strength is translating complex physical-layer algorithms (OFDM, 802.11, 802.15.4) into bit-accurate FPGA pipelines and robust embedded drivers, enabling >32 Gbps processing and GHz-class SDR platforms. Based in Bavaria, he pairs entrepreneurial initiative with deep hardware-software integration skills often sought for cutting-edge wireless protocol development.
11 years of coding experience
7 years of employment as a software developer
Master’s Degree, Telecommunications Engineering, Master’s Degree, Telecommunications Engineering at Universidad Politécnica de Cartagena
Spanish, English, GermanProgramming languages (1)
Github contributions (5)
Pablo-Leyva/RTIMULib-Arduino
Mar 2017 - May 2018
Contributions:4 commits, 7 pushes, 1 branch in 1 year 2 months
Pablo-Leyva/vhdl-axi-stream
Jan 2020 - May 2021
Helper functions and interface definitions for vhdl developed axi stream modules.
Contributions:2 PRs, 6 pushes, 3 branches in 1 year 4 months
axiaxi-streamvhdldefinitionsstream
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