Parker Ridd
Senior Silicon RTL Design Engineer at Microsoft
Minneapolis, Minnesota, United States
Summary
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Senior🎓
Top SchoolParker Ridd is a Senior Silicon RTL Design Engineer with 12 years of experience designing power- and test-focused RTL for high-performance SoCs, currently driving silicon infrastructure and System Fuse Controller IP at Microsoft. He combines hands-on SystemVerilog architecture with Python-driven testbenches and automation, and has a track record of improving RTL modularity and debug flows from his prior SoC work at Intel. Parker pairs rigorous engineering with practical tooling—maintaining documentation sites with Hugo/Azure, mentoring new hires, and accelerating ramp-up with concise reference materials. His background in FPGA reliability research and a history of speeding a large open-source project ninefold reveal a knack for performance tuning across hardware and software. Now also a J.D. candidate, he brings a rare mix of technical depth and emerging legal training that positions him well for policy, IP, or compliance-facing engineering roles.
12 years of coding experience
7 years of employment as a software developer
High School Diploma, High School Diploma at The Woodlands High SchoolBS in Computer Engineering CET-Electrical/Computer Engineering Minor in Spanish Minor in Computer Science, BS in Computer Engineering CET-Electrical/Computer Engineering Minor in Spanish Minor in Computer Science at Brigham Young University
English, Spanish
Github Skills (2)
fpga1
computer-engineering1
Programming languages (1)
Github contributions (5)
BYUCS340/Catan
Jan 2016 - Apr 2016
Settlers of Catan Implementation for BYU CS340-MJGC group
Contributions:3 releases, 250 commits, 38 PRs in 2 months
settlers-of-catansettlerscatanbyu
pbridd/lzrw1-compression-core
Oct 2017 - Dec 2017
Contributions:118 commits, 4 pushes in 1 month
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