Pasquale Schiavone
Scientist at OpenHW Group
Geneva, Geneva, Switzerland
Summary
🤩
Rockstar🎓
Top SchoolPasquale Davide Schiavone is a scientist and RISC-V hardware-software engineer with nine years of experience building low-power heterogeneous SoCs and industrial-grade open-source IP. Currently a Scientist at EPFL and Director of Engineering at the OpenHW Group, he combines postdoctoral research on X-HEEP microcontrollers and ASIC implementations with hands-on embedded design work—evidenced by contributions to the widely used PULPissimo platform for peripheral integration, bootflow, and debug. He earned a PhD from ETH Zurich and has implemented multiple SoCs across 65–16nm nodes to explore accelerators like CGRAs, near-memory computing and POSIT arithmetic for milliwatt-class devices. Comfortable moving between silicon, firmware and tooling, Pasquale brings both academic rigor and production-oriented engineering to open-source processor ecosystems. An early career background in embedded product development and even pastry work hints at practical versatility and an eye for detail.
9 years of coding experience
4 years of employment as a software developer
Network Administrator, Network Administrator at ASSOCAM Scuola CameranaDoctor of Philosophy (PhD) Information Technology and Electrical Engineering, Doctor of Philosophy (PhD) Information Technology and Electrical Engineering at ETH ZürichMaster's degree Computer Engineering - Embedded Systems track, Master's degree Computer Engineering - Embedded Systems track at Politecnico di Torino
Italian, English, French
Github Skills (11)
bootloader10
risc-v10
embedded10
debug10
verilog10
jtag10
systemverilog10
sys10
boot10
testbench8
testbed8
Programming languages (10)
Github contributions (5)
pulp-platform/pulpissimo
Feb 2018 - May 2021
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
Role in this project:
Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:67 commits, 4 PRs, 58 pushes in 3 years 3 months
Contributions summary:Pasquale primarily contributed to the hardware aspects of the PULPissimo platform, focusing on the interaction with peripherals and the debugging infrastructure. Their commits included fixing pin configurations for the camera interface, adding a JTAG testbench, and merging PMP SDK. Furthermore, the user implemented the correct handling of the boot process and tested the WFI wakeup sequence using abstract debug commands and program buffer to interact with the core. These actions indicate a focus on integrating software and hardware to enable the core's operation.
pulpcpusocdomainelectrical-engineering
davideschiavone/cv32e40p
Feb 2020 - Jan 2024
RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
Contributions:22 PRs, 250 pushes, 103 branches in 3 years 11 months
risc-vcpuriscvriscv32risc
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