Patrick Lehmann
VHDL FPGA Expert And Consultant, Continuous Integration Specialist For EDA Toolchains
Bötzingen, Baden-Württemberg, Germany
Summary
🤩
Rockstar🎓
Top SchoolPatrick Lehmann is a VHDL and FPGA specialist with 11 years of hands-on experience designing high-speed digital systems, leading FPGA teams, and integrating EDA toolchains into Git- and web-based CI workflows. As vice-chair of the IEEE P1076 working group he helped shape upcoming VHDL language revisions and contributes to notable open-source projects like the GHDL simulator and the vendor-neutral PoC-Library. At PLC2 he architects end-to-end systems from PCB and FPGA through FreeRTOS to 40G Ethernet, teaches VHDL and verification, and runs CI for complex hardware design flows. His work uniquely blends deep language-standard expertise with practical delivery—developing BIST-driven prototype scaling, CI scripts for multi-platform toolchains, and verification IP integration. Based in Germany, he pairs academic research roots with customer-facing consulting and training, making him a bridge between standardization, open source, and industrial FPGA deployment.
11 years of coding experience
9 years of employment as a software developer
Master of Science - MSc, Computer Science, Discontinued, Master of Science - MSc, Computer Science, Discontinued at Technische Universität Dresden
German, English, French
Stackoverflow
15,832reputation
1.5mreached
296answers
144questions
python-sphinx
top-5%
Github Skills (20)
simulation10
simulations10
vhdl10
powershell10
git9
python-sphinx9
build-system9
compiler-compiler9
version-control9
compiler9
testing7
fpga6
pcie6
clock6
xilinx6
Programming languages (22)
Github contributions (5)
ghdl/ghdl
May 2017 - Jan 2023
VHDL 2008/93/87 simulator
Role in this project:
Backend Developer
Backend DeveloperContributions:70 reviews, 412 commits, 196 PRs in 5 years 8 months
Contributions summary:Patrick primarily focused on enhancing the PowerShell-based build flow for the GHDL simulator, addressing missing files and improving pre-compile scripts for various platforms, including Intel FPGA support and the integration of UVVM verification IPs. They contributed to the underlying codebase by implementing additions to the standard library, specifically including `std_logic_misc` for all VHDL versions in the Synopsys flavor. Furthermore, the user fixed a bug in the VCD format and addressed issues in library compilation on Windows due to changes made in the codebase.
vhdlsimulationghdlcompilersimulator
pyTooling/pyTooling.TerminalUI
Dec 2019 - Oct 2022
A set of helpers to implement a text user interface (TUI) in a terminal.
Contributions:3 releases, 2 reviews, 119 commits in 2 years 9 months
cliuser-interfaceconsoletext-user-interfaceterminal-colors
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