Paul Zavalney
Distinguished Engineer - IC Archictecture at Silicon Labs
Austin, Texas, United States
Summary
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Rockstar🎓
Top SchoolPaul Zavalney is a distinguished semiconductor architect with over two decades of experience designing digital systems and SoCs for IoT wireless products, now leading IC architecture at Silicon Labs. He combines hands-on RTL design and verification expertise with system-level IP and module architecture, driving product-ready silicon from concept through integration. His open-source contributions to RISC-V projects (notably core verification and CV32E40P CSR/debug extensions) reveal a practical focus on reliable debug, performance monitoring, and test automation. Based in Austin, he blends leadership roles and deep engineering craft—moving between manager and principal/architect positions—to ship complex, production semiconductor solutions. Colleagues rely on him for solving subtle RTL and verification challenges that unlock robust device-level features in constrained IoT environments.
6 years of coding experience
27 years of employment as a software developer
Electrical Engineer, Devices and Materials, Electrical Engineer, Devices and Materials at The University of Texas at Austin
Github Skills (17)
debugging10
debug10
systemverilog10
uvm10
risc-v10
cpu10
verification10
sys10
systemverilog-hdl10
embedded10
test-automation10
hardware-designs9
verilog9
fpga8
architecture7
Programming languages (7)
Github contributions (5)
openhwgroup/cv32e40p
Mar 2020 - Nov 2020
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Role in this project:
Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:12 reviews, 39 commits, 28 PRs in 7 months
Contributions summary:Paul focused on modifying and extending the RISC-V processor's CSR (Control and Status Registers) functionality. They implemented debug trigger logic, including adding new CSRs related to triggers and breakpoint matching. The user also addressed illegal instruction exceptions by generating them when accessing unimplemented or blocked CSRs. Their work involved modifying the register file and decoder to handle hardware performance monitor features.
risc-vcpupulpuvmriscv
openhwgroup/core-v-verif
Apr 2020 - Sep 2020
Functional verification project for the CORE-V family of RISC-V cores.
Role in this project:Embedded Systems Engineer / Test Automation Engineer
Embedded Systems Engineer / Test Automation EngineerContributions:1 review, 18 commits, 13 PRs in 4 months
Contributions summary:Paul primarily contributed to the functional verification of a RISC-V core within the `openhwgroup/core-v-verif` repository. Their work included adding and modifying testbench components, specifically integrating debug signals from the memory model and the core testbench. Further contributions involved updating firmware for core tests, enabling performance counters, and adding tests to validate debugger functionality. These changes indicate a focus on testing and verifying the correct operation of the core, especially the debug features.
risc-vsystemverilogriscverificationcores
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