Summary
Pavel Poliansky is an ASIC project manager and technical lead with 10+ years delivering FPGA and embedded hardware systems from concept to production across telecom, medical, and IoT domains. He combines hands-on Verilog/FPGA design and C firmware development with disciplined project management—calendar/resource planning, budget and risk mapping, and Scrum/Kanban delivery—for teams of 5–8 engineers. Pavel has led complex projects such as STM-16 multiplexers, DRFM receivers, and multi-device IoT platforms, often turning ideas into prototypes within months under tight deadlines. He pairs deep tooling expertise (Quartus, Vivado, ModelSim, Altium, Matlab/Simulink, Keil) with practical supply-chain savvy, maintaining direct relationships with Chinese manufacturers to accelerate procurement. An experienced interviewer (500+ candidates) and public speaker, he mentors teams while continuing to code and experiment—recently expanding into Python and 3D printing customization. His profile blends technical depth, rapid prototyping discipline, and a proven track record of shipping hardware-software integrated products.
10 years of coding experience
12 years of employment as a software developer
Master's degree, Radioelectronic systems, Master's degree, Radioelectronic systems at Московский Государственный Институт Радиотехники, Электроники и Автоматики (Технический Университет) (МИРЭА)
Английский