Pepijn De Vos
Software Engineer at Wishful Coding
Enschede, Overijssel, Netherlands
Summary
🤩
Rockstar🎓
Top SchoolPepijn De Vos is a versatile full-stack software engineer with 16 years of experience bridging high-level functional programming and low-level hardware design. Based in Enschede, he contributes to prominent open-source projects—such as ModelingToolkit.jl for SciML and the Yosys/nextpnr FPGA toolchain—where he has added symbolic parameter support, Gowin FPGA features, and synthesis enhancements. He co-founded ChipFlow, ran a long-running solo consultancy for experimental projects, and recently joined GDSFactory, combining entrepreneurial grit with product-focused engineering. Trained in integrated circuit design (MSc) and electrical engineering, he uniquely blends analog/electronics know-how with backend systems and embedded tooling. Colleagues describe him as constantly learning and shipping “crazy” projects, often tackling edge cases that make complex toolchains robust in practice.
16 years of coding experience
4 years of employment as a software developer
Master's degree, Integrated Circuit Design, Master's degree, Integrated Circuit Design at University of TwenteAventurijnHacker, Computer Science, Hacker, Computer Science at Recurse Center
Stackoverflow
4,183reputation
443kreached
39answers
68questions
Github Skills (55)
verilog10
computer-algebra10
symbolic-computation10
javascript10
c-language10
python10
simulator10
css10
mathematics10
synthesis10
yosys10
complex-numbers10
math10
hardware10
vhdl10
Programming languages (40)
Github contributions (5)
YosysHQ/nextpnr
Nov 2019 - Jul 2022
nextpnr portable FPGA place and route tool
Role in this project:
Backend Developer
Backend DeveloperContributions:11 reviews, 22 commits, 16 PRs in 2 years 8 months
Contributions summary:Pepijn primarily contributed to the core functionality of the `nextpnr` project, focusing on the development of the Gowin target. Their work included implementing features related to loading wires, adding slice and IOB (Input/Output Buffer) bels, and integrating timing information, crucial for FPGA place and route. They also made significant changes to the cell definitions, packing logic, and synthesis scripts, improving the tool's ability to support Gowin's FPGA architecture. These contributions indicate a focus on expanding the tool's capabilities.
fpganextpnr
YosysHQ/yosys
Sep 2019 - Jul 2022
Yosys Open SYnthesis Suite
Role in this project:Back-end Developer
Back-end DeveloperContributions:9 reviews, 50 commits, 14 PRs in 2 years 10 months
Contributions summary:Pepijn primarily focused on enhancing the Gowin FPGA synthesis suite, Yosys. Their contributions include integrating features specific to Gowin FPGAs, such as adding splitnets, supporting MUX and BRAM initialization, and refining tristate buffer implementation. They also addressed issues related to unused outputs and implemented improvements, demonstrated by fixing TCL scripts and adding test cases. These changes optimized the toolchain for the Gowin platform.
yosys
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