Peter Hin is a quantitative trader at Jane Street with 11 years of multidisciplinary engineering experience spanning software, FPGA hardware, embedded systems and data science. He combines production trading expertise with deep systems knowledge—having implemented full-system Linux support and RISC‑V features in the widely used gem5 simulator and contributing to its V21.0 release. Comfortable across the stack, his toolset ranges from Node.js and React Native to TensorFlow/PyTorch and CUDA C++, and he has hands-on Verilog and Vivado experience on Zynq/Cyclone FPGAs. Past roles include developing CV algorithms at SenseTime and building FPGA accelerators and device controllers in research and industry, demonstrating a knack for bridging algorithmic ideas to silicon. He also has a proven record shipping production backend systems on AWS and creating low‑level firmware and bootloader modifications—skills that help him reason about latency, reliability and debugging at every layer. Based in Hong Kong, he pairs quantitative trading instincts with an engineer’s curiosity for open-source systems and hardware-software co-design.
11 years of coding experience
3 years of employment as a software developer
Bachelor's degree, Electrical and Electronics Engineering with a Second Major in Business, CGPA 4.93 / 5, Bachelor's degree, Electrical and Electronics Engineering with a Second Major in Business, CGPA 4.93 / 5 at Nanyang Technological University
A levels, General Paper, Project Work, Economics, Mathematics, Physics, Chemistry, Chinese Language, A,A,A,A (Top in cohort),A,A,A, A levels, General Paper, Project Work, Economics, Mathematics, Physics, Chemistry, Chinese Language, A,A,A,A (Top in cohort),A,A,A at Raffles Institution
Secondary, Secondary at St. Paul's Co-educational College (Hong Kong)
The official repository for the gem5 computer-system architecture simulator.
Role in this project:
Back-end Developer
Contributions:5 commits in 3 months
Contributions summary:Peter primarily contributed to the development of RISC-V architecture support within the gem5 simulator, focusing on features related to remote GDB debugging, and later adding a complete FS Linux configuration. They implemented CSR register support in RISC-V remote GDB, which involved adding GDB XML files and modifying register caching mechanisms. Further contributions included the generation of a device tree blob (DTB) and fixes to the CPU switching and PLIC for improved checkpoint restoration.
Contributions:3 releases, 37 commits, 35 pushes in 1 month
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