Peter Monsson
Senior Design Verification Engineer
Copenhagen, Capital Region of Denmark
Summary
👤
Senior🎓
Top SchoolPeter Monsson is a Senior Design Verification Engineer with 14 years of experience delivering digital ASIC and FPGA designs from whiteboard concept to tape-out across process nodes from 0.18µm to 16nm. He combines deep RTL and verification expertise (SystemVerilog, SVA, UVM/VMM) with practical software engineering experience to reduce debug time and keep projects on schedule. His track record includes six taped-out ASICs, high-performance superscalar pipeline and floating-point datapath design, and area- and delay-optimized implementations down to a few hundred gates. A resident UVM mentor and contributor to UVM releases, he brings systematic CDC and verification planning practices that make tape-outs predictable. Based in Copenhagen, he has operated successfully as an independent consultant and in senior roles at Marvell, Analog Devices and Kandou, emphasizing early RTL quality improvements to accelerate time-to-market. Colleagues rely on him when a chip must ship on schedule with high quality.
14 years of coding experience
6 years of employment as a software developer
High School Diploma, Mathematics, High School Diploma, Mathematics at Amtsgymnasiet i RoskildeTook courses for BSCS, Computer Science, Took courses for BSCS, Computer Science at Purdue UniversityTechnical University of Denmark
English, Danish, German
Stackoverflow
103reputation
7kreached
0answers
1question
Github Skills (28)
verilog10
systemverilog10
simulator10
saas10
systemc10
verilator10
lint10
cpp10
rails9
ruby-on-rails8
ruby7
visio6
methodology6
windows6
verification5
Programming languages (6)
Github contributions (5)
PeterMonsson/verilator
Dec 2019 - Apr 2023
Verilator open-source SystemVerilog simulator and lint system
Contributions:20 PRs, 45 pushes, 5 branches in 3 years 4 months
simulatorsystemveriloglintverilator
PeterMonsson/svunit
Feb 2022 - Nov 2023
Contributions:3 PRs, 64 pushes, 17 branches in 1 year 8 months
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